![]() While there are a number of different ways that one may implement a circuit which behaves much like a double-edge flip flop, such circuits generally add some timing constraints which are different from those associated with flip flops.įor example, a simple approach is to have a module combining two 2-input xors and a pair of "T" flip flops (where the state of the input when a clock pulse arrives indicates whether that clock edge should toggle the output), one triggered by a rising edge and one triggered by a falling edge. ![]() As Dave Tweed notes, unless an FPGA includes flip flop hardware which can operate on both edges of a clock, it will be necessary to write your own logic to implement the desired behavior using conventional single-edge flip flops.
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